Towards Next Generation of Robust and Trustable Embedded Systems

Purpose and goal

The main goal of the project was to monitor the system behavior and propose solutions to tolerate faults in Network-based Systems-on-Chip. Another goal was to maintain the system performance while tolerating faults. Optimization was another goal of the project concerning power and performance. Other goals of the project were to analyze the solutions analytically and extending the solutions to other dimensions. We extensively worked on these goals, suggested solutions and connected different works to each other.

Expected results and effects

We studied different fault models and proposed solutions to tolerate faults in different components of the network separately. We connected the solutions to tolerate faults in different components as a single solution. We proposed mapping solutions to map tasks to the system cores and to minimize the congestion in the network. Later, we utilized the mapping strategy to perform the test in the network. We developed analytical formulation to estimate latency in 3D networks with adaptive routing.

Planned approach and implementation

For monitoring the system behavior, we implemented a full-system cycle-accurate visualization framework, called VisualNoC. This simulator is able to record all events in the network including the behaviors of routers, processing elements and packets. It can find bugs, deadlocks, bottlenecks and report statistics such as throughput, latency, utilization etc. Through this simulator, different algorithms and mapping algorithms can be examined and analyzed. Many of our works are implemented on this simulator. We have also used other publicly available tools as necessary.