Atomic Layer Etching for sub 10 nm semiconductor manufacturing - Proof of Concept
Purpose and goal
The project is a Proof-of-Concept where we want to show that our patented method for creating a topological Atomic Level Etching (ALE) mask of semiconductor components meets the requirements of the semiconductor industry. In addition that the method can be used to significantly lower the cost of producing components with a very small pitch. We also need to show that the method scales up to industrial volumes in an existing process environment with acceptable electrical and mechanical properties.
Expected results and effects
- Demonstrated that our method works as expected for structures below 50 nm and then also below 20 and 10 nm respectively in the modern equipment we now have access to. -Identified, tested and modeled industrial parameters as far as possible on laboratory equipment. -Started discussions with industry partners about setting up the process on an industrial basis.
Planned approach and implementation
- Set up and calibrate processes and process verification: set up etching processes for ALE in a world-class ALE equipment. -Testing and varying critical process parameters on laboratory equipment in order to find strengths, weaknesses and general characteristics of our method. -Modeling the process and studying the relationship between process simulation and experiment. Develop a model that allows deeper understanding of the mechanism, and provides feedback to the experimental part.