Integrated WLAN power amplifier with high efficiency and high linearity in 28 nm CMOS

Purpose and goal

The goal of the project goal has been to develop a high-efficiency and linear power amplifier (PA) in 28 nm CMOS for the 802.11ac WiFi standard according to a new amplifier concept, integrating it with a complete 28 nm CMOS transceiver, and evaluating the performance of a manufactured circuit. We have developed a working new PA concept that increases the efficiency by 40% during transmission and with retained linearity. We have shown that it seems robust to be used in a product. However, within the time frame we have not been able to manufacture or evaluate any circuit.

Expected results and effects

The project has demonstrated an amplifier concept that leads to better power amplifiers with lower power consumption than conventional designs. We have also gained a better understanding of how to integrate WLAN-PA with transceivers that can meet the high requirements of the 802.1ac standard, and verified that the critical blocks of the circuit have good reliability. The results are communicated at scientific conferences and journal papers. The project partner Catena plans a test circuit with a delay of 1-1.5 years, which will lead to an improved product.

Planned approach and implementation

The project has followed a conventional design cycle of an integrated circuit: concept work, implementation, layout and design verification, manufacture on external silicon media, encapsulation, evaluation of performance and comparison with existing products. Because of difficulties with the concept, implementation and circuit simulation tools and methods, we did not reach beyond construction/layout. The remaining parts of the project will, however, be carried out with 1-1.5 years delay.