EUREKA-CATRENE Dynamic ULP
| Reference number | |
| Coordinator | ACREO SWEDISH ICT AB - Acreo Swedish ICT AB, Kista |
| Funding from Vinnova | SEK 12 648 000 |
| Project duration | December 2011 - December 2014 |
| Status | Completed |
Purpose and goal
The purpose of the project is to establish a design platform for next-generation CMOS system-on-chip designs at Acreo and ST-Ericsson. The design environment will then be used to develop circuit designs and SOI methodologies to support ST-Ericsson for future chipset platforms based on CMOS SOI semiconductor processes. Using the technology, Acreo will implement high speed digital interfaces as well as analog and RF transceiver blocks which can support ST-Ericsson´s product roadmap. The circuit blocks will be demonstrated in the final year with a dedicated demonstration platform.