Towards a cost effective high quality 5 qubit device (Q High-5)

Purpose and goal

The expected project results are summarized as follows: Development of 5 qubit logic structures Fabrication of wafer scale 5 qubit architectures Validation of designs Deployment of new QiB5 product line The final goal of the project would be the development of a packaged 5 qubit chip which can perform quantum logic operations. The TRL level would go from a technology validated in relevant environment (TRL 5 with the validated QiB0 devices) to a 5 qubit device prototype demonstrated in operational environment (TRL 7 with the QiB5).

Expected effects and result

The QiB5 would facilitate the mass deployment of a high-performance, affordable, and standardized mechanism for industry and academia to test qubit logic enabling rapid and transformative development of novel software architectures.

Planned approach and implementation

The project is divided into 4 work packages where the project timeline and work breakdown structure are shown in the Gantt chart in Figure 5. WP 1 consists of project management. WP2 consists of fabrication of the QiB2 followed by the QiB5. WP3 consists of low temperature validation of designs. WP4 consists of business development and marketing the product to potential clients.