A 5G/6G Analog-to-Digital Converter

Important results from the project

PhD student Hamid Karrari and postdoctoral fellow Siyu Tan started the project by designing an ADC core with a sampling rate of up to 0.5GS/s and a resolution of 10 effective bits. These objective were achieved through a major effort. The ADC core was then used in a time-interleaved ADC, where 4 ADC cores working in sequential time slots realize an ADC with a 4 times higher sampling rate than the individual ADC core, i.e. 2GS/s. The most accurate simulations that can be run on the circuit show that it should be feasible to maintain the nominal resolution up to a sample rate of 1.6GS/s.

Expected long term effects

The project has been carried out largely according to plans, despite some delay due to the lingering effects of the pandemic. A further complication was introduced by the advanced 22nm CMOS process, which showed a significant discrepancy between simulations before and after layout extraction. It should be added that the ADC itself is a very complex system, where extensive auxiliary circuits must be housed on the same silicon wafer as the ADC, for example an input buffer and a memory to store the ADC output. After extensive work, the ADC could be sent to fabrication in November 2022.

Approach and implementation

The time-interleaved ADC was designed starting from an existing successive approximation (SAR) ADC-core, whose maximum sampling frequency was increased by segmenting its internal capacitance array into two parts that work simultaneously, though not on the same signal (pipelining). Between the first part´s output and the second´s input is placed a dynamic amplifier for optimal performance. The linearity of the ADC was increased through a better input buffer and a more powerful sampling switch. An extra bit in the capacitance array enables an easier signal post-processing.